Synopsys Design Compiler Tutorial 2021

report_timing -delay_type min -max_paths 5 > $report_dir/timing_hold.rpt

Let’s walk through a practical session using a simple 32-bit RISC-V processor (e.g., rv32i_core.v ). We’ll target a library (simulated in the tutorial).

Once constraints are applied, you run the optimization engine. For basic designs, the structural compilation is straightforward. For advanced designs, explicit architectural flags are passed. synopsys design compiler tutorial 2021

This has walked you through the complete lifecycle of a synthesis run: from setting up 90nm libraries to generating a final DDC database. The 2021 version of DC is a workhorse—reliable, fast, and incredibly deep.

symbol_library : Used for graphical schematic viewing ( .sdb files). The 2021 version of DC is a workhorse—reliable,

# Analyze the RTL source files for syntax and structural correctness analyze -format sverilog top_module.v sub_module1.v sub_module2.v # Elaborate the top-level design architecture elaborate top_module # Set the current design focus to the top module current_design top_module # Ensure all instances are correctly linked to the libraries link Use code with caution. Phase 2: Defining Environment and Constraints

Pro tip for 2021: Use dc_shell -64bit -legacy_ui if you prefer the classic Tcl prompt over the new Python-driven interface. For basic designs

Load the design into memory and convert the RTL into a Generic Technology (GTECH) netlist.

# Define a clock named 'sys_clk' on port 'clk' with a 10ns period (100 MHz) create_clock -name sys_clk -period 10.0 [get_ports clk] # Model clock uncertainty (skew, jitter, margin) set_clock_uncertainty 0.25 [get_clocks sys_clk] # Model clock transition times set_clock_transition 0.15 [get_clocks sys_clk] Use code with caution. Input and Output Delays

After compilation completes, you must check if your constraints were met. Never skip this validation step. Generating Reports